The present invention relates to a semiconductor device and a method for manufacturing this semiconductor device. In particular, it relates to a semiconductor device provided with common lines that provide electrical continuity for electrode pads that handle a common signal among a plurality of electrode pads provided on a semiconductor element and to a method for manufacturing this semiconductor device.
FIG. 6 is a schematic drawing that illustrates an example from the prior art. This semiconductor device is constituted of an LOC (lead-on-chip) structure, and is provided with a chip-type semiconductor element 1, a plurality of leads L and common lines 2a' and 2b' connected via an insulating tape T on the semiconductor element 1.
In addition, of the plurality of electrode pads, electrode pads P1 source supply are connected with the common line 2a' through bonding wires W, and electrode pads P2 for ground are connected with the common line 2b' through bonding wires W. Through these connections, the common line 2a' constitutes a source supply line and the common line 2b' constitutes a ground line.
Furthermore, electrode pads Pa and Pb are connected with the common line 2a' which constitutes the source supply line via bonding wires W, and electrode pads Pc, Pd, Pe and Pf are connected to the common line 2b' which constitutes the ground line through bonding wires W. It is to be noted that other electrode pads are directly coupled with leads L through bonding wires W.
In recent semiconductor devices, miniaturization of the semiconductor element 1 has necessitated extremely fine internal wiring. Because of this, if the connections of the electrode pads P1 for source supply and the electrode pads P2 for ground are implemented within the semiconductor element 1, degradation in performance characteristics will occur due to a reduction in voltage. Therefore, they are wired electrically, utilizing the common lines 2a' and 2b'.
However, such a semiconductor device presents the following problem. Namely, when the electrode pads P and the leads L are coupled through the bonding wires W, as shown in FIG. 7(a), it is necessary to loop the wires over the common lines 2a' and 2b', allowing a sufficient clearance H in order to avoid contact with them.
Normally, the common lines 2a' and 2b' are formed as lead frames that are integrated with the leads L, and their thickness is set at approximately 150 micrometer. Thus, it becomes necessary to allow approximately 400 micrometer or more for the loop height of the bonding wires W in order to ensure that it does not make contact with the common lines 2a' and 2b'.
However, if the loop height is set high in this manner, when forming a thin package PC as shown in FIG. 7(b), a problem occurs in that the bonding wires are not contained within the package PC and become exposed.